The present invention relates to methods for separating a wafer for integrated circuit apparatuses with dielectrics. More particularly, the present invention relates to a methods of separating, with dielectrics a junction separation type wafer for integrated circuit apparatuses.
Among conventional integrated circuit apparatuses, junction separation type wafers are usually used for separating the work potential of the circuit elements or the circuit parts from each other utilizing a reversely biassed pn junction for preventing the circuit elements or the circuit parts from interfering each other.
However, since the parasitic effects of known built-in transistors or diodes often cause trouble such as latching-up etc., and mindful that operation interferences often interfere with each other, dielectrics separation type wafers, especially the above described joined substrate type wafers, have been utilized within the context of integrated circuit apparatuses for high frequency use. Such devices are particularly suited to applications contingent upon high reliability over time.
Utilizing dielectrics separation type wafers to separate the semiconductors into a plurality of mutually separated semiconductor regions shows that this is quite effective when done with dielectrics. Particular interest has been shown this approach among known devices, however, prominent difficulties remain.
The prominence of the extant difficulties, pertaining to prior art methods for separating conventional wafers with dielectrics, among the devices of the prior art is demonstrated by reference to FIGS. 3(a) to 3(f).
FIGS. 3(a) to 3(f) show a conventional dielectrics separation type wafer according to the prior art. However, significant issues remain unaddressed among the devices of the prior art.
FIG. 3(a) is a sectional view showing a joined substrate dielectrics type wafer shown generally at 10 to be separated with dielectrics. The joined substrate type wafer 10 includes a semiconductor substrate 11, and an (n) type semiconductor substrate 13 jointed at high temperature onto substrate 11 through an insulation film 12, which contains silicon oxide and similar insulating material. Substrate 13 is lapped to a predetermined thickness and mirror polished.
The dielectrics separation of the wafer 10 is conducted as follows. Referring to FIG. 3(b), trenches 20 are dug by anisotropic etching, using an etching mask of oxide film, from the surface of semiconductor substrate 13 down to the insulation film 12 to divide substrate 13 into a plurality of semiconductor regions 14.
Referring to FIG. 3(c), the entire surface of wafer 10 including trenches 20 is covered with dielectrics film 21 by thermal oxidation or similar methods which are known to those having a modicum of skill in the art.
Subsequently, a poly-crystalline silicon 30 is grown on dielectrics film 21 by the CVD method to a predetermined thickness so as to completely fill the trenches 20 with the poly-crystalline silicon 30. Refer to FIG. 3(d).
The deposition of the dielectrics film 21 and the growth of the poly-crystalline silicon 30 are conducted over the entire surface of the wafer 10. Thereafter, excess poly-crystalline silicon 30 is removed from the surface of wafer 10 by the etching back method. Refer to FIG. 3(e).
The dielectrics separation type wafer 50 of FIG. 3(f) is completed by removing the dielectric film 21 from the surface of the semiconductor regions 14 leaving an extension 22 of the dielectric film 21 in the immediate vicinity of trench 20, along the perimeter (periphery) of trenches 20. This step is undertaken to treat the entire surface of wafer 10, except the inside of each trench 20. This step involves an dry etching technique known as etching back, and includes removing the dielectrics film 21 from the upper surface of the semiconductor regions 14. Refer to FIG. 3(f). Circuit elements or circuit parts of the integrated circuit are distributed and built in semiconductor regions 14 which are insulated from each other on the wafer 50.
Longstanding problems remain to be solved by the subject matter of the present invention. Although the dielectrics separation type wafer according to the prior art shows a moderate separation performance in terms of reducing the parasitic effects (or interference), a major drawback is that among conventional integrated devices, the circuit elements or parts should be completely isolated and immune from the parasitic effects (interferences) from neighboring parts.
Prior art attempts to reduce the parasitic effects have included insulating the semiconductors regions 14 from each other. However, unstable operations or oscillations of conventional separation type wafers have, on occasion, interfered with the operations of conventional separation type wafers. Indeed, prior art attempts have generally been unsuccessful in shielding individual regions from interferences from other semiconductor regions.
The present inventor has discovered that the instability of prior art integrated devices results from the parasitic effects discussed above. Indeed, the present invention is premised upon the discovery that prior art devices have suffered substantial interference from neighboring semiconductor regions due, in large part, upon the ineffective insulation between the semiconductor regions 14.
The present inventor has also discovered additional defects which contribute to the general failure of prior an wafers. Such defects include a defective patterning process along the peripheral surface of the semiconductor region 14 in the extension 22 of the dielectrics film 21, which generally extending out of the trench 20, along its periphery.
Referring now to FIG. 4, a sectional view showing an upper part of the trench 20 is shown. When the upper surface of extension 22 is rough, then in patterning extension 22 by dilute hydrofluoric acid using a photoresist film as a masking M, the echant (i.e., dilute hydrofluoric acid) E can penetrate the masking M and erode extension 22.
In the worst case scenario, echant E can penetrate semiconductor region 14 and seep into the poly-crystalline silicon 30 in trench 20 and erode the upper part of the dielectrics film 21.
In an attempt to overcome his drawback, prior art has contemplated patterning extension 22 by an etching process exemplified by plasma etching. This process improves somewhat the insulation between the semiconductor regions 14 but is not completely effective.
However, the present inventor has discovered that the rough appearance of the, upper surface of extension 22 is caused primarily by the matrix of the poly-crystalline silicon 30, which contains crystal grains of varying sizes. The grain size distribution pattern in the poly-crystalline silicon matrix is transferred (copied) to the dielectrics film 21, which, in turn, has been implicated in causing the rough upper surface generally associated with conventional extension 22.
In order to address these longstanding problems, the present invention provides a method of separating a semiconductor wafer with dielectrics. The present invention solves the problems described above which are inherent in known disclosures.
Further, prominent among the drawbacks of known dielectrics separation type wafers are the overall production costs. The present invention likewise reduces the overall cost of the dielectric separation processes, thus enhancing the economic utility of applicants' teachings.